Integrated circuits having adjacent P-type doped regions having shallow trench isolation structures without liner layers therein therebetween

ABSTRACT

An integrated circuit substrate includes first and second adjacent p-type doped regions spaced-apart from one another. A trench in the integrated circuit substrate is between the first and second adjacent p-type doped regions. An insulator layer in the trench has a side wall, wherein the side wall is free of a layer that reduces a stress between the integrated circuit substrate and the insulator layer.

CLAIM FOR PRIORITY

[0001] This application is a divisional of application Ser. No.10/021,165, filed Dec. 7, 2001 which claimed priority to Korean PatentApplication No. 2000-74915, filed on Dec. 9, 2000, the entiredisclosures of which are incorporated herein by reference.

FIELD OF THE INVENTION

[0002] The present invention relates to integrated circuits and methodsof forming integrated circuits in general and, more particularly, toshallow trench isolation structures in integrated circuits and methodsof forming shallow trench isolation structures in integrated circuits.

BACKGROUND OF THE INVENTION

[0003] With the development of semiconductor manufacturing techniques,progress has been made in increasing the speed and integration ofsemiconductor devices. Local Oxidation Of Silicon (LOCOS) layers havebeen used as isolation layers in semiconductor devices. However, LOCOSmay promote a bird's beak effect at the edges of the isolation layerthus reducing the size of the adjacent active regions and which mayadversely affect current leakage.

[0004] Referring to FIG. 1, a semiconductor substrate 10 includes as acell region, a core region and a peripheral region. A blocking pattern(not shown) is formed on the semiconductor substrate 10 to expose anisolation region. The blocking pattern may be a stack of an oxide layerand a silicon nitride layer. The exposed semiconductor substrate 10 isetched to a depth using the blocking pattern as a mask to form trenchest₁ and t₂. The trench t₁ is formed in the cell region and the trench t₂is used to define a PMOS transistor region in the core and peripheralregions. The trenches t₁ and t₂ can be formed by dry etching usingplasma.

[0005] The dry etching may cause silicon lattice defects and damage theinner surfaces of the trenches t₁ and t₂. Conventionally, to reduce suchsilicon lattice defects and damage, a side wall oxide layer 12 can beformed by thermally oxidizing the inner surfaces of the trenches t₁ andt₂. Also, the formation of the side wall oxide layer 12 can remove sharpcorners generated in the trenches t₁ and t₂ associated with the bird'sbeak effect discussed above.

[0006] Subsequently, a silicon nitride liner 14 can be formed on theside wall oxide layer 12. The silicon nitride liner 14 may reduce stressdue to a difference between the respective thermal expansioncoefficients associated with the semiconductor substrate 10 and asilicon oxide layer in the trenches t₁ and t₂.

[0007] A dielectric material, such as a High Density Plasma (HDP) oxide,is deposited on the semiconductor substrate 10 to completely fill thetrenches t₁ and t₂. Next, a Chemical Mechanical Polishing (CMP) processis performed on the HDP oxide and the blocking pattern to expose asurface of the semiconductor substrate 10 to form an STI layer 16 in thetrenches t₁ and t₂ which completes the conventional STI structure.

[0008] However, the semiconductor device having the conventional STIstructure discussed above may cause the following problems. Withreference to FIGS. 2A and 2B, high energy or “hot” carriers in a MOStransistor can penetrate through the side wall oxide layer 12 into theSTI layer 16. N-type charged carriers, such as electrons 30, thatpenetrate into the STI layer 16 may collect at an interface of thesilicon nitride liner 14 and the side wall oxide layer 12 and in thesilicon nitride liner 14 as shown in FIG. 2A. The electrons 30 may betrapped at the interface due the thickness of the side wall oxide layer12. When a dense region of the electrons 30 collects at the interface,positive holes 32 can be induced at a boundary of the STI layer 16opposite the electrons 30 as shown in FIG. 2A.

[0009] As shown in FIG. 2B, a conductive path through the semiconductorsubstrate 10 may not be formed between n-type junction regions 26 a and26 b of an N-channel field effect transistor (N-FET) because the majorcarriers are electrons 30. However, the holes 32 at the boundary of theSTI layer 16 can provide a current path I that electrically connects ap-type junction region 28 a (associated with a gate electrode of a MetalOxide Semiconductor (MOSFET) 24) and 28 b associated with an adjacentMOSFET. Although the STI structure is located between the p-typejunction regions 28 a and 28 b, the leakage current can be increased bythe current path I which can cause, for example, increased standbycurrent after burn-in of the integrated circuit.

[0010] Furthermore, in cases where a channel region of the P-FET isadjacent to the silicon nitride liner 14 where the electrons 30 aretrapped, holes may be induced in the channel region of the P-FET therebyaffecting the operation of the P-FET. Also, holes induced when the P-FETis turned on may not be easily removed and, therefore, may remain afterthe P-FET is turned off. The length of the channel of the P-FET may,therefore, be reduced which may decrease the threshold and breakdownvoltages associated with the P-FET.

SUMMARY OF THE INVENTION

[0011] Embodiments according to the present invention may provideintegrated circuits having Shallow Trench Isolation (STI) structures.Pursuant to these embodiments, an integrated circuit substrate caninclude first and second adjacent p-type doped regions spaced-apart fromone another in the integrated circuit substrate. A trench in theintegrated circuit substrate is between the first and second adjacentp-type doped regions. An insulator layer in the trench has a side wall,wherein the side wall is free of a layer thereon that reduces a stressbetween the integrated circuit substrate and the insulator layer.

[0012] In some embodiments according to the present invention, adielectric material is in the trench directly on the side wall. In someembodiments according to the present invention, the trench is a firsttrench and the side wall is a first side wall and the insulator layer isa first insulator layer. First and second adjacent n-type doped regionsare spaced-apart from one another in the integrated circuit substrate. Asecond trench is in the integrated circuit substrate between the firstand second adjacent n-type doped regions. A second insulator layer inthe second trench has a second side wall. A liner layer on the secondside wall can reduce a stress between the integrated circuit substrateand the second insulator layer.

[0013] In some embodiments according to the present invention, thedielectric material is a first dielectric material and a seconddielectric material is in the second trench on the liner layer. In someembodiments according to the present invention, the side wall is free ofsilicon nitride. In some embodiments according to the present invention,the integrated circuit includes a core region, a peripheral region, anda cell region that is spaced apart from the core and peripheral regionsand has a greater density of integrated circuit devices therein than thecore and peripheral regions, wherein the first trench is in one of theperipheral and core regions. The second trench is in the cell region.

[0014] In some embodiments according to the present invention, theintegrated circuit includes a core region, a peripheral region, and acell region that is spaced apart from the core and peripheral regionsand has a greater density of integrated circuit devices therein than thecore and peripheral regions. The trench is between the core andperipheral regions and the cell region.

[0015] In some embodiments according to the present invention, theintegrated circuit includes a core region, a peripheral region, and acell region that is spaced apart from the core and peripheral regionsand has a greater density of integrated circuit devices therein than thecore and peripheral regions. The trench is in one of the core andperipheral regions.

[0016] Pursuant to method embodiments according to the presentinvention, first and second adjacent p-type doped regions are formedspaced-apart from one another in an integrated circuit substrate. Atrench is formed in the integrated circuit substrate between the firstand second adjacent p-type doped regions. An insulator layer is formedin the trench having a side wall, wherein the side wall is free of alayer that reduces a stress between the integrated circuit substrate andthe insulator layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017]FIG. 1 is a cross-sectional view of a semiconductor device havinga conventional STI structure therein.

[0018]FIG. 2A is a cross-sectional view illustrating an NMOS transistoradjacent to an n-type region having a conventional STI structuretherebetween.

[0019]FIG. 2B is a cross-sectional view illustrating a PMOS transistoradjacent to an p-type region having a conventional STI structuretherebetween.

[0020]FIGS. 3A through 3E are cross-sectional views that illustrateintegrated circuits and methods of forming integrated circuits having anSTI structure according to embodiments the present invention.

[0021]FIGS. 4 through 6 are cross-sectional views that illustratesintegrated circuits and methods of forming integrated circuits havingSTI structures according to embodiments of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS ACCORDING TO THE INVENTION

[0022] The present invention now will be described more fullyhereinafter with reference to the accompanying drawings, in whichembodiments of the invention are shown. This invention may, however, beembodied in many different forms and should not be construed as limitedto the embodiments set forth herein; rather, these embodiments areprovided so that this disclosure will be thorough and complete, and willfully convey the scope of the invention to those skilled in the art.

[0023] In the drawings, the thickness of layers and regions areexaggerated for clarity. It will be understood that when an element suchas a layer, region or substrate is referred to as being “on” anotherelement, it can be directly on the other element or intervening elementsmay also be present. When an element is disclosed as being “directly on”another element, no intervening elements are present. Althoughembodiments according to the present invention are disclosed herein withreference to semiconductor substrates, it will be understood thatembodiments according to the present invention may utilize any type ofintegrated circuit substrate. Like numbers refer to like elementsthroughout.

[0024] Referring to FIG. 3A, a pad oxide layer 102 and a silicon nitridelayer 104 are formed on a semiconductor substrate 100. The semiconductorsubstrate 100, which can be a silicon substrate containing impurities,is defined as having a cell region in which memory devices can be formedand core and peripheral regions in which PMOS transistors can be formed.According to FIG. 3A, A1 denotes the cell region and A2 denotes the coreand peripheral regions.

[0025] In some embodiments according to the present invention, the padoxide layer 102 is formed to a thickness in a range between about 70 and160 Ångstroms and the silicon nitride layer 104 is formed in a rangebetween about 1300 and 1600 Ångstroms. The silicon nitride layer 104 andthe pad oxide layer 102 are etched using known photolithographyprocesses, to expose a pre-isolation region of the semiconductorsubstrate 100 thereby forming a blocking pattern. Herein, “pre-isolationregion” means a region for defining the cell, core and peripheralregions and the isolation structures formed in respective regions.

[0026] The first and second trenches 106 a and 106 b are formed byetching the semiconductor substrate 100 to a depth in a range betweenabout 0.1 and 1.5 μm and preferably to a depth in a range between about0.24 and 0.26 μm using the blocking pattern as a mask. The first andsecond trenches 106 a and 106 b are used to form Shallow TrenchIsolation (STI) structures. The first trench 106 a can provide isolationbetween devices formed in the cell region A1 and the second trench 106 bcan provide isolation between devices formed in the core and peripheralregions A2.

[0027] The first trench 106 a is formed in the cell region A1 which maybe densely populated with devices. Accordingly, the width of the firsttrench 106 a may be less than the width of the second trench 106 b thatis formed in the core and peripheral regions A2. The first and secondtrenches 106 a and 106 b may be formed using dry etching in conjunctionwith a plasma. The dry etching may cause silicon lattice defects anddamage to the surfaces of the first and second trenches 106 a and 106 b.For example, dry etching may cause the formation of sharp corners at thebottom of the side walls in the first and second trenches 106 a and 106b.

[0028] According to FIG. 3B, a side wall oxide layer 108 is formed inthe first and second trenches 106 a and 106 b by thermally oxidizing theinner surfaces of the first and second trenches 106 a and 106 b. Theside wall oxide layer 108 may address the silicon lattice defects andthe damage to the first and second trenches 106 a and 106 b. Forexample, the side wall oxide layer 108 may smooth the sharp corners atthe bottom of the side walls of the first and second trenches 106 a and106 b. In some embodiments according to the present invention, the sidewall oxide layer 108 is formed to a thickness in a range between about20 and 240 Ångstroms and more preferably in a range between about 20 and50 Ångstroms.

[0029] A relief liner 110 is formed on the side wall oxide layer 108.The relief liner 110 may relieve a stress caused by a difference betweenthe respective thermal expansion coefficients associated with thesilicon semiconductor substrate 100 and a dielectric in the trenches 106a and 106 b. The relief liner 110 may also reduce the penetration ofdefects into the first and second trenches 106 a and 106 b. In someembodiments according to the present invention, the relief liner 110 isa silicon nitride layer or a silicon oxynitride layer either of whichcan be formed to a thickness in a range between about of 50 and 100Ångstroms.

[0030] According to FIG. 3C, a photoresist pattern 112 is formed on thecell region using a known photolithography process. The core andperipheral regions A2 are exposed. The relief liner 110 on the core andperipheral regions A2 is removed so that the side wall oxide layer 108is free of the relief liner 110 thereon. In some embodiments accordingto the present invention, it is preferable that the relief liner 110 isetched using isotropic etching. In some embodiments according to thepresent invention, the isotropic etching is a wet etching using aphosphoric acid solution or a dry etching using an isotropic gas.

[0031] According to FIG. 3D, the photoresist pattern 112 is removed by aknown method. A dielectric layer 114 is formed on the resultantsemiconductor substrate 100 to a thickness of more than about 6000Ångstroms to fill the first and second trenches 106 a and 106 b. In someembodiments according to the present invention, the dielectric layer 114is a HDP dielectric layer having good filling properties. The dielectriclayer 114 is densified to reduce the upper part of the dielectric layer114 in the trenches 106 a and 106 b lost during a subsequent CMPprocess. In some embodiments according to the present invention, thedensification process is performed at a temperature higher than about900° C.

[0032] According to FIG. 3E, a CMP process is performed on thedielectric layer 114, the relief liner 110, the silicon nitride layer104, and the pad oxide layer 102 until the surface of the semiconductorsubstrate 100 is exposed, thereby providing the first and second STIstructures 120 a and 120 b.

[0033] According to the present embodiment, the relief liner 110 of thesecond STI structure 120 b in the core and peripheral regions A2 isremoved. As a result, an amount of negative charges trapped at the inneredge of the second STI structure 120 b can be reduced thereby reducingthe positive charges induced at the outer edge of the second STIstructure 120 b. As a result, a leakage current path may not begenerated between adjacent p-type doped regions 204 of adjacent PMOStransistors.

[0034] The region and size of the second STI structure 120 b in the coreand peripheral regions A2 may be larger than the first STI layer 120 ain the cell region. Consequently, less stress may be caused by adifference in respective thermal expansion coefficients associated withthe substrate and a silicon oxide layer in the trench even though athermal process is performed. Therefore, although the second STIstructure 120 b is free of the relief liner 110, the stress on thesecond STI layer 120 b may be reduced during the thermal process.

[0035] In further embodiments according to the present invention, thesecond STI structure 120 b is formed only between PMOS transistors inthe core and peripheral regions. In addition, the first STI structure120 a (having the relief liner 110 included) is formed in the cellregion as well as in a region for providing isolation in areas that arenot between PMOS transistors in the core and peripheral regions.

[0036] In these further embodiments according to the present invention,the manufacturing method is substantially the same as that disclosedabove in reference to FIGS. 3A to 4, except that the photoresist pattern112 for removing the relief liner 110 is formed to define trenches onlybetween adjacent PMOS transistors. The other steps may be the same asthose disclosed above. According to FIG. 5, reference numeral A3 denotesa region where circuits other than PMOS transistors are formed in thecell region, the core region and the peripheral region. Referencenumeral A4 denotes a region having PMOS transistors formed therein.

[0037] In some embodiments according to the present invention, asillustrated in FIG. 6, the pad oxide layer 102 and the silicon nitridelayer 104 are formed on the semiconductor substrate 100. Ananti-reflection film 250 is formed on the silicon nitride layer 104 toreduce reflection from the silicon nitride layer 104 during a subsequentphotolithography process. In some embodiments according to the presentinvention, the anti-reflection film 250 is a silicon oxynitride (SiON)layer formed to a thickness in a range between about 600 and 700Ångstroms.

[0038] The anti-reflection film 250, the silicon nitride layer 104, andthe pad oxide layer 102 are etched using a known photolithographyprocess to expose a pre-isolation region of the semiconductor substrate100. The semiconductor substrate 100 is etched to a depth in a rangebetween about 0.1 to 1.5 μm using the silicon nitride layer 104 as amask, to thereby form the first and second trenches 106 a and 106 b. Thefirst trench 106 a is formed in the cell region A1 or in the region A3except for those portions within A3 that provide isolation between PMOStransistors. The second trench 106 b is formed in the core andperipheral regions A2 or the region A4 for providing isolation betweenadjacent PMOS transistors in the core and the peripheral regions.Forming the anti-reflection film 250 on the silicon nitride layer 104may prevent a notching phenomenon in the photolithography process.

[0039] As disclosed above, in embodiments according to the presentinvention, the STI structures that provide isolation between the coreand peripheral regions or between PMOS transistors in the core andperipheral regions, are formed free of the relief liner. The amount ofnegative charges trapped or remaining at the inner boundary of the STIstructure can be reduced which may reduce the amount of positive chargesinduced at the outer boundary of the STI layer. As a result, a currentpath may not be created between the adjacent p-type doped regions ofadjacent PMOS transistors and the threshold and breakdown voltagesassociated with the PMOS transistor can be protected. In contrast, STIstructures formed in the cell region and between adjacent n-type dopedregions include the relief layer.

[0040] In the drawings and specification, there have been disclosedembodiments of the invention and, although specific terms are employed,they are used in a generic and descriptive sense only and not forpurposes of limitation, the scope of the invention being set forth inthe following claims.

What is claimed:
 1. An integrated circuit comprising: an integratedcircuit substrate; first and second adjacent p-type doped regionsspaced-apart from one another in the integrated circuit substrate; atrench in the integrated circuit substrate between the first and secondadjacent p-type doped regions; and an insulator layer in the trenchhaving a side wall, wherein the side wall is free of a layer thereonthat reduces a stress between the integrated circuit substrate and theinsulator layer.
 2. An integrated circuit according to claim 1 furthercomprising: a dielectric material in the trench directly on the sidewall.
 3. An integrated circuit according claim 1 wherein the trenchcomprises a first trench and the side wall comprises a first side walland the insulator layer comprises a first insulator layer, theintegrated circuit further comprising: first and second adjacent n-typedoped regions spaced-apart from one another in the integrated circuitsubstrate; a second trench in the integrated circuit substrate betweenthe first and second adjacent n-type doped regions; a second insulatorlayer in the second trench having a second side wall; and a liner layeron the second side wall that reduces a stress between the integratedcircuit substrate and the second insulator layer.
 4. An integratedcircuit according to claim 3 wherein the dielectric material comprises afirst dielectric material, the integrated circuit further comprising: asecond dielectric material in the second trench on the liner layer. 5.An integrated circuit according to claim 1 wherein the side wall is freeof silicon nitride.
 6. An integrated circuit according to claim 3further comprising: a core region of the integrated circuit substrate; aperipheral region of the integrated circuit substrate; and a cell regionof the integrated circuit substrate that is spaced apart from the coreand peripheral regions and having a greater density of integratedcircuit devices therein than the core and peripheral regions, whereinthe first trench is in one of the peripheral and core regions andwherein the second trench is in the cell region.
 7. An integratedcircuit according to claim 1 further comprising: a core region of theintegrated circuit substrate; a peripheral region of the integratedcircuit substrate; and a cell region of the integrated circuit substratethat is spaced apart from the core and peripheral regions and having agreater density of integrated circuit devices therein than the core andperipheral regions, wherein the trench is between the core andperipheral regions and the cell region.
 8. An integrated circuitaccording to claim 1 further comprising: a core region of the integratedcircuit substrate; a peripheral region of the integrated circuitsubstrate; and a cell region of the integrated circuit substrate that isspaced apart from the core and peripheral regions and having a greaterdensity of integrated circuit devices therein than the core andperipheral regions, wherein the trench is in one of the core andperipheral regions.
 9. An integrated circuit comprising: an integratedcircuit substrate; a core region of the integrated circuit substrate; aperipheral region of the integrated circuit substrate; a cell region ofthe integrated circuit substrate that is spaced apart from the core andperipheral regions and having a greater density of integrated circuitdevices therein than the core and peripheral regions; a first trench inone of the peripheral and core regions of integrated circuit substrate;a first insulator layer in the first trench having a first side wall,wherein the first side wall is free of a layer that reduces a stressbetween the integrated circuit substrate and the first insulator layer;a second trench in cell region of the integrated circuit substrate; asecond insulator layer in the second trench having a second side wall;and a liner layer on the second side wall that reduces a stress betweenthe integrated circuit substrate and the second insulator layer.
 10. Anintegrated circuit according to claim 9 wherein the first trench islocated between first and second adjacent p-type doped regions andwherein the second trench is located between first and second adjacentn-type doped regions.
 11. An integrated circuit according to claim 9further comprising: a first dielectric material in the first trenchdirectly on the first side wall; and a liner layer on the second sidewall that reduces a stress between the integrated circuit substrate andthe second insulator layer; and a second dielectric material directly onthe liner layer.
 12. A semiconductor device having a shallow trenchisolation (STI) structure, comprising: a semiconductor substrate havinga plurality of trenches therein that provide isolation between a cellregion of the semiconductor substrate that includes memory devicestherein and core and peripheral regions of the semiconductor substrateincluding a PMOS transistor; a side wall oxide layer on inner surfacesof the plurality of trenches; a relief liner on the side wall oxidelayer of at least one trench in the cell region; and a dielectricmaterial in the plurality of trenches.
 13. A semiconductor deviceaccording to claim 12 wherein the side wall oxide layer has a thicknessof about 20 to 240 Å.
 14. A semiconductor device according to claim 12wherein the relief liner comprises a silicon nitride layer or a siliconoxynitride layer.
 15. A semiconductor device according to claim 12wherein the dielectric material comprises a high density plasmadielectric layer.
 16. An integrated circuit comprising: a liner layer onside walls of first isolation trenches located in a cell region of anintegrated circuit substrate to provide stress relief between adielectric in the first isolation trenches and the substrate; and secondisolation trenches located in a peripheral region of the substratehaving side walls that are free of the liner layer.
 17. An integratedcircuit according to claim 16 wherein the first isolation trenches arenarrower than the second isolation trenches.
 18. An integrated circuitaccording to claim 16 wherein the first isolation trenches have a depthin a range between about 0.1 μm and 1.5 μm.
 19. An integrated circuitaccording to claim 16 wherein the liner layer comprises one of a siliconnitride layer and a oxynitride layer having a thickness in a rangebetween about 50 Å and about 100 Å.